manuais Encore SIM EDITOR SOFTWARE

Encore SIM EDITOR SOFTWARE Guia do Utilizador (449 páginas)

Marca: Encore | Categoria: Software | Tamanho: 5.51 MB |

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Índice

VirSim User Guide

1

VirSim

3

User Guide

3

Contents

5

About this Manual FIX ME!

23

Licensing

24

Audience

24

Platforms

25

Other Sources of Information

25

X Resources

26

SOLV-IT! Online Help

27

Customer Support

27

About this Manual

28

VirSim Overview 1

29

Operation Modes

30

Advantages of VirSim

31

VirSim Overview

32

Key Terms and Concepts

33

OSF/Motif™ environment

34

VirSim Windows

35

VirSim Navigation

44

Selecting Signals

46

Drag-and-drop Operation

47

Linking Windows

49

Figure 1-9 Linking Window

50

Accelerator Keys

51

Operation Accelerator

52

HB WW SW LB RW IW

52

Starting VirSim 1

55

Starting VirSim

56

+cfgfile+<filename>

57

+vslogfile+<filename>

57

<signal>)

57

+cfgfile+default.cfg

60

VHDL Command Line Syntax

62

Figure 2-2 Command Line

66

Opening the Open File Dialog

71

Figure 2-3 Open File Dialog

72

Open Files

72

Opening a Single History File

76

Closing History Files

77

Reopening History Files

79

Saving a Configuration File

81

Loading a Configuration File

82

Configuration File Format

83

Nested Configuration Files

84

Loading Sources

85

Hierarchy Browser 1

89

Selecting a Design

91

Choosing View Options

92

Hierarchy Browse

93

Navigating the Hierarchy

94

Adding Signals to a Group

97

Hierarchy Browser

100

Menu Bar

101

File Menu

101

Edit Menu

102

Display Menu

102

View Menu

103

Waveform Window 1

105

Waveform Window

106

Signal Value Pane

108

Waveform Pane

110

Cursor Pane

111

Status Bar

112

Selecting and Viewing Signals

113

Adding and Reordering Signals

113

User Defined Buses

117

Zooming Waveforms

118

Note:

121

Delta Cycles

123

Expand and Collapse Times

124

View Delta Cycles

125

Advanced Features

127

Expressions

128

Creating Breakpoint Groups

128

Changing the Display Format

133

Selecting Drawing Mode

134

Modifying Waveform Height

135

Additional Features

140

Printing Waveforms

142

Printing a Time Range

143

Specifying a Printer Name

145

Printing to Postscript

145

Toolbar and Menu Reference

147

Context Sensitive Menus

150

Zoom Menu

156

Source Window 1

159

Execution Pane

161

Source Text Pane

162

Control Pane

163

Table 5-2 Control Pane

164

Source Window

165

Navigate and View a Design

166

Edit the Correct Design File

167

Follow Source Execution

169

Control Source Execution

169

Using Breakpoints

169

Set Breakpoints

169

Clear Breakpoints

170

Run to Breakpoints

170

Using Instance Groups

171

Define Markers

174

Capture Line Data

175

Descend Instance

179

Go to Parent

179

Logic Browser 1

185

Introducing the Logic Browser

186

Getting Started

188

Viewing Graphic Objects

189

Logic Browser

190

Logic Browse

191

Navigating a Design

194

Using Event Origin

198

Using the Connection Dialog

198

Expressions Example

201

Changing the Display

203

Toolbar and Menu Reference

205

Next Selected

206

Signals Change

206

Logic Browser CSM

207

Prev/Next Change

208

Load View NL

208

Edit At Definition

208

Module Instance CSM

209

Port Instance CSM

210

Event Origin

211

Load Value

211

View Connection

211

Selected Net CSM

212

Register Window 1

217

What is a View?

218

Which Signals are Loaded?

219

Edit Views

220

Undo Command

221

Display Unique Events

222

Set Time Scale

222

Align Objects

223

Distribute Objects

223

Register Window

226

Signal Properties CSM

228

Select All

230

Graphics Menu

234

Interactive Window 1

237

History Pane

238

Command Prompt

238

User-Defined Buttons

239

Simulator Controls

239

Step Control

239

Scope Control

240

Time Display

240

Window Status

241

Interactive Window

242

Simulation

243

Controlling the Simulator

245

Breakpoint Durations

246

Expression Breakpoints

247

Line Breakpoints

250

Default Buttons Files

252

Creating User-Defined Buttons

253

Defining a Button

254

Selection Substitution

255

File Commands

257

Edit Commands

257

Sim Commands

258

Project Window 1

261

Project Window

262

What is a Workspace?

263

What is a Project?

264

What is a Design Top?

264

Workspace Pane

265

View Pane

269

Project Folder View

270

Design Top Folder View

271

Source File Folder View

272

Dependency Folder View

274

Library Folder View

275

New VHDL Library

277

New Verilog Library Work

277

New Verilog Library Other

277

Library View

278

Add Top

279

Edit Source

279

View Full Detail

279

Tear Off Windows

280

Output Pane

280

Project Menu

285

Tools Menu

287

Windows Menu

288

New Workspace Dialog

289

Open File Dialog

291

Add Files Dialog

293

Select a Directory Dialog

295

Edit Setup Constants Dialog

296

New Verilog Library Dialog

298

Library Name

298

Path Name

298

Using the Options Dialog

299

Options Dialog Buttons

300

Setting Analyze Options

301

Setting Elaborate Options

302

Setting Simulate Options

304

Setting Verilog Run Options

306

Commands

308

Files and Directories

314

Moving Projects

315

Using a Makefile

316

Time Units 1

317

Display Unit

318

Time Units

319

Radices 1

321

Radix Dialog

323

Radix Editor

324

Mapping List Editor

325

Creating a User-Defined Radix

326

Event Origin 1

327

Before Using Event Origin

328

How to Use Event Origin

329

Display the Event Origin

331

Debug with Event Origin

334

Building Buses 1

337

Building Buses

338

Bus Builder Dialog

339

Markers 1

345

Marker knownOk set

346

Markers Dialog

347

Opening the Marker Dialog

349

Creating a Marker

349

Deleting a Marker

349

Editing a Marker

350

Setting a Marker

350

Expressions 1

353

Expressions Dialog

354

Entering Signal Names

358

Creating Expressions

359

Updating Expressions

360

Displaying Expressions

361

Trigger Types

362

Searching with Expressions

363

Level Sensitive Searches

364

Edge-triggered Searches

365

VirSim Setup 1

367

Caution: Before You Start

368

VirSim Platforms

368

Common Settings

370

Mouse Button Setting

371

VirSim Setup

372

Waveform Window Settings

374

Source Window Settings

376

Hierarchy Window Settings

377

Logic Browser Settings

378

Register Window Settings

379

Interactive Window Settings

380

Settings for X Resources

381

X Color System

382

Switching Color Maps

383

VCD+ (vpd) File Generation 1

385

Advantages of VCD+

386

System Tasks and Functions

387

$vcdpluson;

388

$vcdplusoff

389

$vcdplusautoflushon

390

$vcdplusautoflushoff

390

VCD+ (vpd) File Generation

391

Syntax for Specifying MDAs

392

Examples

394

Note: Unlimited dimensions

395

Starting bound:

396

Ending bound:

396

mem01[2][5][8]

400

Selected element:

400

$vcdplusmemorydump Task

401

Execution Data

401

Execution

402

Source Statement System Tasks

403

$vcdplustraceon

403

Simulator Run-Time Options

408

VCD+ Methodology

411

C1> sigon_instreg;

414

VCD+ On/Off PLI Rules

415

Performance Tips

416

Translating VCD and VCD+ 1

419

<vpd_file>

420

EVCD Options

421

Translating VCD and VCD+

422

VCD file in ASCII format

423

VHDL Mapping

424

Viewing OpenVera Assertions 1

427

Viewing OpenVera Assertions

428

How Sequences Are Tested

429

Viewing OVA Results in VirSim

431

Waveform Defaults 2

435

Waveform Defaults

436

Waveform Style: VHDL Defaults

438

Chapter 16

439

Table A-2 VHDL Defaults

439

Waveform Style: EPIC Defaults

440

Encore SIM EDITOR SOFTWARE Guia do Utilizador (140 páginas)

Marca: Encore | Categoria: Software | Tamanho: 7.30 MB |

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Índice

User Guide

1

Bluetooth QD ID B015987

2

LIMITED WARRANTY STATEMENT

4

3. WHAT LG WILL DO:

5

4. STATE LAW RIGHTS :

5

5. HOW TO GET WARRANTY

5

SERVICE :

5

Table of Contents

7

Your Phone

11

Rear View

12

Getting Started

13

Charging your phone

15

Installing a Memory Card

15

On-Screen Icons

17

General Functions

19

Answering a Call

20

Adjusting the Volume

20

Setting Proﬁles

20

Vibrate only Mode (Quick)

21

Entering Text

22

123 Mode (Numbers Mode)

23

Using the Symbol Mode

23

Using the T9 Mode

23

Using the ABC Mode

24

Using the 123 (Numbers) Mode

25

T9 Dictionary

25

Using the Korean Mode

25

Address Book

26

New Contact

27

Speed Dials

28

SIM Management

29

Service Dial Numbers

29

In-Call Menu

30

Video Share Calling

31

Answering a Video Share Call

34

Video Player

35

Conference Calls

36

Your Standby Screen

38

The Quick Keys

39

Favorite

40

Shortcuts

42

Annunciator

42

Menu Tree

44

Messaging

45

Message folders

49

Standard View

50

Conversation View

50

Message settings

52

Multimedia Message

53

Voicemail Number

53

Service Message

53

Communications

54

Offline Menu

55

IM Information

56

Online Menu /

56

1-to-1 conversation

56

General Options

56

Conversation screen

59

PicDial

60

Mobile Web

61

YPmobile

62

AT&T Navigator

63

Wikimobile

65

My-Cast Weather

65

AppCenter

66

Color Graphics

67

Answer Tones

67

MEdia Net Home

67

AT&T Music

68

Adding Music To Your Handset

69

Purchasing and downloading

70

Music directly to your Device

70

Transferring Music from the

71

Digital Music Service

71

Transferring Music using

71

Windows Media Player

71

Drag and Drop Music Using

72

As A Mass Storage

72

Changing USB Connection

73

Settings

73

Deleting Music Files

73

Additional Music Services

74

Warning

76

Applications

77

Camera

78

Settings Menu

80

Record Video

81

Camera Album

82

My Stuff

83

Memory Card

84

Other Files

84

Answer Mode

87

Minute Minder

87

Call Waiting

87

Call Reject

87

Send DTMF Tones

87

Bluetooth

88

Shop Tones

90

Ringtone

90

Message Tone

91

Alert Tone

91

Multimedia

91

Power On/Off Tones

91

Voice Recorder

93

Voice Command

94

Calendar

97

World Clock

98

Stopwatch

99

Calculator

100

Tip Calculator

100

Unit Converter

100

Date & Time

101

Tools and Settings

102

Connection

105

Start Up Guide

105

Touch Calibration

106

Application Settings

106

Software Update

109

Phone Information

109

Accessories

111

For Your Safety

112

Memory card information and

113

FCC RF Exposure Information

113

Body-worn Operation

114

Part 15.105 statement

114

Cautions for Battery

115

Battery Disposal

115

Adapter (Charger) Cautions

115

Avoid damage to your hearing

115

Safety Guidelines

116

Tips on Efficient Operation

117

Electronic Devices

117

Pacemakers

117

Hearing Aids

117

Safety Information

119

Charger and Adapter Safety

120

Battery Information and Care

120

Explosion, Shock, and Fire

120

General Notice

121

FDA Consumer Update

122

10 Driver Safety Tips

129

Consumer Information on

132

SAR (Speciﬁc Absorption

132

Glossary

134

Encore SIM EDITOR SOFTWARE Guia do Utilizador (1492 páginas)

Marca: Encore | Categoria: Software | Tamanho: 10.00 MB |

Inglês

Índice

User Guide

1

Contents

3

Getting Started 1

47

Getting Started

48

What VCS Supports

49

Main Components of VCS

49

Preparing to Run VCS

52

Obtaining a License

53

Setting Up Your Environment

54

Setting Up Your C Compiler

55

VCS Workflow

56

Coverage Metrics User Guide

57

% vcs mem.v cpu.v

58

Basic Compile-Time Options

60

Running a Simulation

64

Basic Runtime Options

65

Modeling Your Design 1

69

Avoiding Race Conditions

70

Flip-Flop Race Condition

72

Counting Events

74

Time Zero Race Conditions

75

Conditional Compilation

77

Combining the Techniques

81

and more

91

Case Statement Behavior

92

Memory Size Limits in VCS

93

Using Sparse Memory Models

93

Obtaining Scope Information

95

Modeling Your Design

100

Avoiding Circular Dependency

101

Dealing With Unassigned Nets

103

Code Values at Time 0

104

Signal Value/Strength Codes

106

Compiling Your Design 1

109

Using the vcs Command

110

Incremental Compilation

111

Triggering Recompilation

112

Using Lint

118

+lint=GCWM,NCEID

119

+lint=none

120

Enabling the Checking

123

Filtering Out False Negatives

124

HSOPT Technology

126

Condition

128

+cliecho +no_pulse_msg

129

+sdverbose +vcs+finish

129

Performance Considerations

131

Compilation

136

Doing SDF annotation

137

Minimizing Memory Consumption

138

Memory Setup

140

/usr/ccs/bin/sparcv9/ld

141

Using Radiant Technology

142

Known Limitations

143

The Configuration File Syntax

145

Radiant Technology

151

Library Mapping Files

153

Displaying Library Matching

155

Configurations

156

Configuration Syntax

157

Hierarchical Configurations

159

The -top Compile-Time Option

160

Limitations of Configurations

161

Simulating Your Design 1

163

% executable [options]

164

Simulating Your Design

165

Save and Restart

166

Save and Restart File I/O

168

Simulation

170

Improving Performance

174

Profiling the Simulation

175

CPU Time Views

176

“Moduletime”

181

Memory Usage Views

186

The Program View

189

Example 4-12 Program View

189

DVE Panes

194

Managing DVE Windows

194

Setting Display Preferences

200

VPD and EVCD File Generation

209

Advantages of VPD

210

$vcdplusoff

212

$vcdplusoff(test.risc1.alu1);

213

$vcdplusflush;

213

$vcdplusautoflushon

214

$vcdplusautoflushoff

214

Syntax for Specifying MDAs

215

Note: Unlimited dimensions

219

$vcdplusmemon( mem01 );

220

Starting bound:

221

Ending bound:

221

Example 6-6 Selected element:

225

Using $vcdplusmemorydump

226

Execution Data

227

Execution

228

Source Statement System Tasks

229

$vcdplustraceon

229

$vcdplusdeltacycleon;

230

$vcdplusdeltacycleoff;

231

$vcdplusglitchon;

231

$vcdplusglitchoff;

232

Runtime Options

233

+vpdbufsize+nn

234

+vpdfile+filename

234

+vpdfilesize+nn

235

+vpdignore

235

+vpddrivers

236

+vpdnoports

236

+vpdnocompress

236

VPD Methodology

237

VPD On/Off PLI Rules

240

Performance Tips

241

EVCD File Generation

243

VCD and VPD File Utilities 1

245

The vcdpost Utility

246

" out1 [6] $end

247

The vcdpost Utility Syntax

248

The vcdiff Utility

249

The vcdiff Utility Syntax

250

VCD and VPD File Utilities

251

The vcat Utility

256

The vcat Utility Syntax

257

10000 x

258

30 z

258

The vcsplit Utility

267

The vcd2vpd Utility

270

The vpd2vcd Utility

272

The Command file Syntax

274

The vpdmerge Utility

277

Restrictions

279

Value Conflicts

280

Using UCLI

285

UCLI Interactive Commands

286

UCLI Command-Alias File

291

Operating System Commands

291

CLI Commands

294

For example:

298

Traversing Call-stacks

301

Command Files

303

Key Files

305

Post-Processing 2

317

Post-Processing

318

Line Tracing

319

Delta Cycle

319

Race Detection 1

321

Race Detection

322

Enabling Race Detection

324

Conditions

325

The Race Detection Report

325

END RACE REPORT

326

Post Processing the Report

328

#! /usr/local/bin/perl

330

Delays and Timing 1

335

Transport and Inertial Delays

336

Delays and Timing

337

Pulse Control

341

+pulse_e/0 +pulse_r/0

347

Specifying the Delay Mode

354

SDF Backannotation 1

357

Using SDF Files

358

The $sdf_annotate System Task

359

SDF Backannotation

360

Precompiling an SDF File

363

The SDF Configuration File

372

Delay Objects and Constructs

373

MTM=MAXIMUM;

376

379

Example:

381

DEVICE (1:2:3)

385

(INSTANCE CELLTYPE)

387

(ABSOLUTE

387

(DEVICE B (1:2:3))

387

INTERCONNECT Delays

388

Min:Typ:Max Delays

393

+timopt+100ns

396

DONE TIMOPT

397

Editing the timopt.cfg File

399

Editing Clock Signal Entries

400

Negative Timing Checks 1

401

Negative Timing Checks

402

reg clk, d;

414

reg rst;

414

wire q;

414

Checking Conditions

418

How VCS Calculates Delays

420

So the timing checks are now:

425

Timing violation in top.fd1_1

427

SAIF Support 2

429

Using SAIF Files

430

SAIF System Tasks

430

$toggle_start();

431

$toggle_stop();

431

$toggle_reset();

431

"rtl_on"

432

"off"

432

"on"

432

System Tasks

433

SAIF Support

434

SWIFT Environment Variables

438

${LD_LIBRARY_PATH}

439

Generating Verilog Templates

440

Using the PLI 2

453

Using the PLI

454

Writing a PLI Application

455

The PLI Table File

458

ACC_capabilities

460

PLI Specifications

461

ACC Capabilities

463

or read

465

or read_write

465

or callback

465

‘celldefine compiler

467

-y and -v compile-time

467

Features

469

or force

471

Using the PLI Table File

472

Enabling ACC Capabilities

473

Configuration File

474

{accWrite};

475

+applylearn+filename

479

Using VPI Routines

481

DirectC Interface 3

489

DirectC Interface

490

Declaring the C/C++ Function

494

Calling the C/C++ Function

500

Converting Strings

505

Avoiding a Naming Problem

507

Using Direct Access

508

Using the vc_hdrs.h File

515

Using Abstract Access

517

Using vc_handle

518

Using Access Routines

519

’b’, ’o’, ’d’, or ’x’

531

This example now displays:

532

The C code is as follows:

537

Same as vc_toInteger

537

U *vc_2stVectorRef(vc_handle)

539

UB *vc_MemoryRef(vc_handle)

544

memcpy(p2,p1,8);

545

p2 += 8;

545

}

545

#define scalar_0 0

560

#define scalar_1 1

560

#define scalar_z 2

560

#define scalar_x 3

560

U vc_mdaSize(vc_handle, U)

564

565

Summary of Access Routines

565

Enabling C/C++ Functions

569

Specifying the DirectC.h File

571

Useful Compile-Time Options

572

Environment Variables

573

Interface 1

577

Usage Scenario Overview

580

Supported Port Data Types

581

Input Files Required

583

The Verilog model is display:

587

Using GNU Compilers on Linux

591

Generating the Wrapper

593

Instantiating the Wrapper

595

Elaborating the Design

597

Use a Stubs File

599

Using a Port Mapping File

602

Debugging the Verilog Code

605

Transaction Level Interface

607

Interface Definition File

609

Transaction Debug Output

613

Instantiation and Binding

614

Miscellaneous

618

Using OpenVera Assertions 1

623

Introducing OVA

624

Using OVA Directives

625

Using OpenVera Assertions

626

OVA Flow

629

Linter General Rule Messages

631

Linter General Rule Messages:

638

OVA Runtime Options

643

OVAPP Flow

647

[-ova_dir directory_path]

648

Directory

654

Viewing Output Results

663

Using the Default Report

664

Command Line Options

667

Inlining OVA in Verilog

670

Specifying Pragmas in Verilog

671

Methods for Inlining OVA

672

//ova_begin

674

//OVA_END

674

//ova bind

675

//ova [(port1, ..., portN)];

675

Checker Library

678

Case Checking

681

// ova parallel_case;

682

// ova full_case;

682

// ova no_case;

682

Use Model

685

Limitations on the Input

686

Recommended Methodology

688

Caveats

688

Post-processing Flow

689

Global Monitoring

692

Name-Based Monitoring

695

(category, action);

696

Task Invocation From the CLI

698

Debug Control Tasks

699

Calls From Within Code

700

$ova_stop system task:

701

$ova_severity_action:

703

OpenVera Native Testbench 1

707

OpenVera Native Testbench

708

OpenVera

709

Other Features

710

Preprocessor Directives

712

Top Level Constructs

713

Program Block

713

"Hello World!"

714

The Template Generator

715

Multiple Program Support

717

Compiling Multiple Programs

719

Example Configuration File

725

Multiple program example:

726

[ntb_compile-time_options]

730

% simv +vcs_runtime_options

730

-ntb_shell_only] tb.vr

732

Top-level Verilog Module

733

% simv +ntb_load=./libtb.so

734

Compile-time Options

735

-ntb_filext .vr

737

-ntb_filext .vr+.vri+.vrl

737

-ntb_incdir ../src1

737

Value Description

744

Reordering

747

Circular Dependencies

749

Encryption

749

Using Encrypted Files

750

Testbench Functional Coverage

751

Measuring Coverage

755

-cg_coverage_control=value

757

Example 21-2

758

Coverage Reporting Flow

760

Mozilla):

761

Solver Choice

767

Temporal Assertions

769

Temporal Assertion Flow

771

Including the Header Files

772

Resetting Assertion

773

Suspending Threads

776

Terminating the AssertEngine

777

Example Testbench

777

Together

781

Scope of Interoperability

782

Data Type Mapping

786

Mailboxes and Semaphores

787

Strings

789

Enumerated Types

789

Integers and Bit-Vectors

792

Structs and Unions

794

Connecting to the Design

795

Miscellaneous Issues

800

Constructs

800

Functional Coverage

801

Testbench Optimization

805

Enabling the NTB Profiler

806

Performance Profiler Example

806

Example 21-11 dpi.c

807

Compile:

808

0.84% of the total time

810

VCS Memory Profiler

811

Note:

817

VCS Memory Profiler Output

818

SystemVerilog Data Types

822

The chandle Data Type

823

User-Defined Data Types

825

Enumerations

825

Methods for Enumerations

826

The $typeof System Function

828

Structures and Unions

830

Structure Expressions

833

SystemVerilog Arrays

834

Multiple Dimensions

835

Indexing and Slicing Arrays

836

Programs

838

Writing To Variables

839

Automatic Variables

841

Multiple Drivers

842

Release Behavior

843

Integer Data Types

844

Unpacked Arrays

846

Structures

847

Using the VPI

848

SystemVerilog Operators

850

New Procedural Statements

851

Statements

852

The do while Statement

854

SystemVerilog Processes

855

The always_latch Block

858

The always_ff Block

858

Tasks and Functions

859

Functions

861

SystemVerilog Packages

866

SystemVerilog DPI

870

#5 i = i/2;

872

endtask

872

Hierarchy

874

New Data Types for Ports

876

Ref Ports on Modules

880

Encapsulation

882

Example 22-5 Basic Interface

884

Using Modports

886

Functions In Interfaces

888

Enabling SystemVerilog

889

Immediate Assertions

892

Sequences

893

Using Repetition

896

Specifying a Clock

899

Value Change Functions

899

Anding Sequences

900

Oring Sequences

901

Conditions for Sequences

902

Sequence

903

Properties

907

Inverting a Property

911

Past Value Function

912

The disable iff Construct

912

Action Blocks

918

The VPI For SVA

922

-ova_debug -ova_dir -ova_file

930

-ova_cov_name -ova_cov_db

931

The report.index.html File

947

The tests.html File

952

The category.html File

952

The hier.html File

953

Assertion System Functions

958

Using Assertion Categories

958

Using Attributes

960

VCS Flow for SVTB

967

Testbench Constructs

968

-cm_name filename

970

The string Data Type

971

String Conversion Methods

974

Predefined String Methods

978

Program Blocks

981

Dynamic Arrays

986

The new[ ] Built-In Function

986

The size() Method

988

The delete() Method

988

Associative Arrays

990

Wildcard Indexes

991

String Indexes

991

Associative Array Methods

992

VCS displays the following:

994

Queue Methods

997

The foreach Loop

1000

Constraints

1003

List of Aggregate Methods

1004

Table 24-1

1004

Constructors

1008

Static Properties

1011

Class Extensions

1015

Abstract classes

1016

Polymorphism

1018

The Output of the program is:

1020

Chaining Constructors

1024

Accessing Class Members

1028

Methods

1029

“this” keyword

1030

Class Packet Example

1032

Random Constraints

1034

Constraint Blocks

1035

External Declaration

1038

Inheritance

1038

Set Membership

1039

Weighted Distribution

1041

Implications

1042

Global Constraints

1045

Default Constraints

1046

Variable Ordering

1053

Unidirectional Constraints

1054

Constraint Early Late

1059

Static Constraint Blocks

1065

Randomize Methods

1066

Controlling Constraints

1068

Disabling Random Variables

1071

Output of the above program:

1073

In-line Constraints

1074

In-line Constraint Checker

1075

Random Number Generation

1077

$srandom()

1079

Seeding for Randomization

1081

Random Sequence Generation

1083

RSG Overview

1084

Production Declaration

1085

Production Controls

1088

Weights for Randomization

1088

Aspect Oriented Extensions

1094

Element Description

1104

Precedence

1109

Example 24-14

1116

Example 24-16

1119

Point 1: Value = 5

1123

Point 2: Value = 5

1123

Point 3: Value = 6

1123

Output is: 6

1123

Examples

1126

Examples of advice code

1128

Example 24-23 :

1128

Example 24-26

1130

Array manipulation methods

1131

Array locator methods

1133

Array reduction methods

1139

Semaphores

1143

Semaphore Methods

1145

Mailboxes

1146

Mailbox Methods

1148

Waiting for an Event

1149

Persistent Trigger

1150

Merging Events

1151

Reclaiming Named Events

1152

Event Comparison

1153

Clocking Blocks

1154

input #0 i1;

1156

`timescale 1ns/1ns

1157

Input and Output Skews

1159

Hierarchical Expressions

1160

Clocking Block Events

1162

Default Clocking Blocks

1162

Cycle Delays

1163

Input Sampling

1164

Synchronous Events

1165

Synchronous Drives

1165

Drive Value Resolution

1166

Virtual Interfaces

1173

Scope of Support

1174

Virtual Interface Modports

1174

Array of Virtual Interface

1177

Clocking Block

1178

Event Expression/Structure

1179

Null Comparison

1179

Coverage

1180

The covergroup Construct

1181

Defining a Coverage Point

1183

Bins for Value Ranges

1183

Bins for Value Transitions

1187

Defining Cross Coverage

1189

Defining Cross Coverage Bins

1190

Cumulative Coverage

1192

Instance-based Coverage

1193

Coverage Options

1193

Predefined Coverage Methods

1196

Output of the program is:

1200

Unified Coverage Reporting

1203

The Coverage Report

1204

The ASCII Text File

1204

The HTML File

1206

Post-Processing Tools

1207

Test Name Database

1208

Loading Coverage Data

1209

-cm_dir and -cm_name will

1211

-cm_dir directory_path_name

1211

VCS NTB (SV) Memory Profiler

1212

UCLI Interface

1213

CLI Interface

1213

Incremental Profiling

1214

Only Active Memory Reported

1214

Declaration :

1217

Limitations

1219

Include Files

1219

SystemVerilog File

1222

Source Protection 1

1223

Source Protection

1224

Encrypting Source Files

1225

Encrypting Specified Regions

1226

option:

1229

Encrypting SDF Files

1231

Simulating Encrypted Models

1234

Using System Tasks

1235

Writing PLI Applications

1235

Mangling Source Files

1236

-Xmangle=4 option:

1239

-Xmangle=12 option:

1240

-Xmangle=28 option:

1242

Creating A Test Case

1245

[, module_identifier...]

1246

VCS Environment Variables A

1249

VCS Environment Variables

1250

VCS_LIC_EXPIRE_WARNING 5

1252

VCS_LIC_EXPIRE_WARNING 0

1252

Compile-Time Options B

1253

% vcs top.v toil.v +v2k

1254

Compile-Time Options

1255

Options for SystemVerilog

1261

.SystemClock (SystemClock)

1265

.adder_inp1 (inp1)

1265

.adder_inp2 (inp2)

1265

Options for Debugging

1269

-cm line+cond+fsm+tgl

1276

-cm_cond basic+allops

1277

+vcdfile+filename

1283

-f -gen_asm -gen_obj

1290

-line -l -u -v -y

1290

Executable

1291

Options for Pulse Filtering

1292

Options for PLI Applications

1293

Timing Checks

1294

SmartModels

1297

+lint=[no]ID

1298

+warn=[no]ID

1299

Options for Cell Definition

1300

Options for Licensing

1301

-cc compiler

1303

-CC options

1303

Options for Source Protection

1306

General Options

1310

Enable Verilog 2001 Features

1310

Reduce Memory Consumption

1310

TetraMAX

1311

Specifying a VCD File

1311

Specifying a Log File

1312

Hardware Modeling

1313

Defining a Text Macro

1313

For Long Calls

1314

Simulation Options C

1317

Simulation Options

1318

Options for Coverage Metrics

1326

Options for Recording Output

1329

+sdfverbose

1330

Options for VPD Files

1331

Operations

1334

Options for VCD Files

1334

MIPD Annotation

1339

This appendix describes:

1341

• Compiler Directives

1341

• System Tasks and Functions

1341

Compiler Directives

1342

General Compiler Directives

1348

System Tasks and Functions

1350

System Tasks for VCD Files

1352

System Tasks for VPD Files

1358

Commands

1367

System Tasks for Log Files

1367

System Tasks for File I/O

1369

System Tasks for Time Scale

1372

System Tasks for PLA Modeling

1376

Checks for a Plusarg

1379

SDF Files

1379

Counting the Drivers on a Net

1380

Depositing Values

1380

PLI Access Routines E

1383

PLI Access Routines

1384

Parameter Value

1421

1426

*filename)

1429

int tag)

1437

No return value

1438

VCS API Routines

1467

$fseek D-30

1471

Encore dispositivos